Heap/stack guard pages using a wakeup unit
US8713294B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2010 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Jan 19, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for providing a memory access check on a processor including the steps of detecting accesses to a memory device including level-1 cache using a wakeup unit. The method includes invalidating level-1 cache ranges corresponding to a guard page, and configuring a plurality of wakeup address compare (WAC) registers to allow access to selected WAC registers. The method selects one of the plurality of WAC registers, and sets up a WAC register related to the guard page. The method configures the wakeup unit to interrupt on access of the selected WAC register. The method detects access of the memory device using the wakeup unit when a guard page is violated. The method generates an interrupt to the core using the wakeup unit, and determines the source of the interrupt. The method detects the activated WAC registers assigned to the violated guard page, and initiates a response.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.