Controller interface providing improved data reliability
US8713404B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2011 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | May 28, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one implementation, a memory device includes non-volatile memory, a memory controller communicatively coupled to the non-volatile memory over a first bus, and a host interface through which the memory controller communicates with a host device over a second bus. The memory device can also include a signal conditioner of the host interface adapted to condition signals to adjust a signal level of signals received over the second bus based on signal level data received from the host device, wherein the signal level data relates to a voltage level of signals generated by the host device to encode data transmitted across the second bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.