Encoding and/or decoding memory devices and methods thereof
US8713411B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2008 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Apr 2, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/05
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Encoding/decoding memory devices and methods thereof may be provided. A memory device according to example embodiments may include a memory cell array and a processor including at least one of a decoder and an encoder. The processor may be configured to adjust a redundant information rate of each channel, where each of the channels is a path of the memory cell array from which data is at least one of stored and read. The redundant information rate may be adjusted by generating at least one codeword based on information from a previous codeword. Therefore, example embodiments may reduce an error rate when data is read from and written to the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.