Synthesizing VHDL multiple wait FSMS into RT level FSMS by preprocessing
US8713494B2 · kind B2 · utility
0Cited by
2References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2013 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Jun 13, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Preprocessing parallel sequences of “wait” statements and synthesizing these multiple “wait” statements to construct support for RTL tools. This is accomplished by preprocessing a VHDL process with multiple wait statements (referred to as BehFSM) into an equivalent register transfer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.