Tools and methods for yield-aware semiconductor manufacturing process target generation
US8713511B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2012 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Sep 17, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit having at least one array of circuit cells, each circuit cell having a plurality of transistors each performing a specified function, the transistors having predefined performance parameter margins for the specified function, the circuit cells designed by providing at least one operating condition for the circuit cell; providing a value of sigma over a predefined range; determining for each transistor, at least one variable transistor characteristic, which is defined by a semiconductor process that results in transistors having such transistor characteristics; providing an array of instances based upon the value of the sigma and using a design of experiments factorial calculation; providing a metric of interest by which to deter-nine pass/fail instances; extracting individual pass/fail instances for the metric of interest; and determining a yield for the array of circuit cells for the targeted operating condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.