SOI lateral MOSFET devices

US8716794B2 · kind B2 · utility

Assignee

• University of Electronic Science and Technology of China · CN

Inventors

• Xiaorong Luo · Chengdu, CN
• Florin Udrea · Cambridge, GB

Key dates

• Filing date: Aug 10, 2010
• Grant date: May 6, 2014
• Expiry date: Oct 4, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/516

Abstract

The present invention relates to a semiconductor power device and power integrated circuits (ICs). The lateral SOI MOSFET in the present comprises a trench gate extended to the dielectric buried layer, one or multiple dielectric trenches in the drift region, and a buried gate in said dielectric trench. The permittivity of the dielectric in said dielectric trench is lower than that of said active layer. Firstly, said dielectric trench not only greatly improves breakdown voltage, but also reduces pitch size. Secondly, the trench gate widens the effective conductive region in the vertical direction. Thirdly, dual gates of said trench gate and buried gate increase channel and current densities. Thereby, specific on-resistance and the power loss are reduced. The device of the present invention has many advantages, such as high voltage, high speed, low power loss, low cost and ease of integration. The device in the present invention is particularly suitable for power integrated circuits and RF power integrated circuits.