Clock diagnosis circuit
US8717066B2 · kind B2 · utility
2Cited by
5References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2012 |
| Grant date | May 6, 2014 |
| Priority date | — |
| Expiry date | Oct 23, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/04
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock diagnosis circuit includes: a delay circuit to delay the clock by a prescribed time which is not more than the clock pulse width; an integral multiplication delay circuit to delay a delayed clock outputted from the delay circuit by a prescribed number of cycles; a first exclusive OR circuit to encode the clock using the delayed clock; a second exclusive OR circuit to decode an output of the first exclusive OR circuit using an output of the integral multiplication delay circuit; and a comparison circuit to compare the clock with an output of the second exclusive OR circuit to thereby detect a malfunction of the clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.