Digital delay line driver
US8717080B2 · kind B2 · utility
4Cited by
15References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 7, 2008 |
| Grant date | May 6, 2014 |
| Priority date | — |
| Expiry date | Nov 2, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00221
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Improved digital delay line driver is described. A delay line driver circuit includes elements to drive the delay line in one or multiple locations to provide a dynamic, adjustable slew rate on the output signal. The delay line driver circuit may also include active elements coupled to the transistors of the delay line to deactivate the delay line transistors substantially simultaneously, rather than cascading in series. Shutting off the delay line transistors substantially simultaneously reduces or eliminates crowbar or shoot through current on an edge transition of the output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.