Non-overlapping clock generator
US8717081B2 · kind B2 · utility
1Cited by
2References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2012 |
| Grant date | May 6, 2014 |
| Priority date | — |
| Expiry date | Jun 11, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/15093
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A non-overlapping clock generator including an enabling module and N pulse-generating modules connected as a ring is provided. When the ith input node has a high voltage level, the enabling module enables the ith pulse-generating module so as to trigger the ith pulse-generating module to discharge the ith input node. After the ith input node has been discharged to a low voltage level, the ith pulse-generating module charges the ith output node to the high voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.