Successive equalizer for analog-to-digital converter (ADC) error correction
US8717209B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2012 |
| Grant date | May 6, 2014 |
| Priority date | — |
| Expiry date | Sep 5, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/44
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various pipeline ADCs are disclosed that substantially compensate for interference or distortion that results from imperfections with various ADC modules of the pipeline ADCs. The pipeline ADCs include various ADC stages and various compensation stages that are coupled to the various ADC stages. The various ADC stages convert their corresponding analog inputs from an analog signal domain to a digital signal domain to provide various digital output signals and various analog residual signals to subsequent ADC stages. The various compensation stages compensate for interference or distortion that is impressed onto the various analog residual signals which results from imperfections within previous ADC stages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.