Successive approximation register analog-to-digital converter
US8717221B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2013 |
| Grant date | May 6, 2014 |
| Priority date | — |
| Expiry date | Feb 8, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/468
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A successive approximation register analog-to-digital converter is provided which includes first and second capacitor arrays configured to generate first and second level voltages, respectively; a comparator configured to compare the first and second level voltages to output a comparison signal; SAR logic configured to generate a digital signal in response to the comparison signal; and a variable common mode selector configured to compare a first analog input voltage and a common mode voltage and to supply one of the first analog input voltage and the common mode voltage to top plates of the first and second capacitor arrays according to a comparison result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.