Reconfigurable multi-level sensing scheme for semiconductor memories
US8717802B2 · kind B2 · utility
15Cited by
18References
20Claims
0Family size
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Key dates
| Filing date | Sep 12, 2011 |
| Grant date | May 6, 2014 |
| Priority date | — |
| Expiry date | May 2, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5634
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for sensing at least one parameter indicative of a logical state of a multi-level memory cell includes the steps of: measuring the parameter of the multi-level memory cell; comparing the measured parameter of the multi-level memory cell with a prescribed reference signal, the reference signal having a value which varies as a function of time; and storing a time value corresponding to a point in time at which the reference signal is substantially equal to the measured parameter of the multi-level memory cell, the stored time value being indicative of a sensed logical state of the multi-level memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.