Floating addressing of an EEPROM memory page
US8717820B2 · kind B2 · utility
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5References
15Claims
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Key dates
| Filing date | Aug 30, 2012 |
| Grant date | May 6, 2014 |
| Priority date | — |
| Expiry date | Aug 30, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for electrically programming a non-volatile memory in which a programming cycle includes prior addressing of memory cells from an initial address corresponding to a first row and a column of a memory plane. The method may include addressing the memory cells in a second consecutive row when the end of the first row is reached to store data on bits with consecutive and increasing addresses in two consecutive rows.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.