Multi channel semiconductor memory device and semiconductor device including the same
US8717828B2 · kind B2 · utility
13Cited by
2References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2011 |
| Grant date | May 6, 2014 |
| Priority date | — |
| Expiry date | May 7, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor memory device that includes a plurality of channel memories mounted within a package and is capable of minimizing or reducing the number of through-silicon vias. With the semiconductor memory device, a row command or a row address on two or more channels is applied through a shared bus. The semiconductor memory device is capable of reducing an overhead of a die size by reducing the number of through-silicon vias. A method of driving a multi-channel semiconductor memory device including a plurality of memories, using a shared bus, is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.