Spread-carrier self-detecting code receiver with summed delay processing and methods for signal acquisition and detection
US8718119B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 19, 2012 |
| Grant date | May 6, 2014 |
| Priority date | — |
| Expiry date | Jun 19, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/7093
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Embodiments of a spread-carrier self-detecting code (SCSDC) receiver with summed-delay processing (SDP) and method are generally described herein. In some embodiments, the SCSDC-SDP receiver is arranged to generate a chip-matched filter output from a received spread-spectrum signal and perform SDP on the chip-matched filter output with a plurality of delay-processing chains. The SDP may include multiplying a conjugated and delayed chip-matched filter output with the chip-matched filter output and applying a code-matched filter that is matched to a delay-multiplied code. The outputs from the code-matched filters of each delay-processing chain may be coherently combined to provide an output having correlation peaks for use generating frequency error and timing information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.