Clock and data recovery (CDR) using phase interpolation
US8718217B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2009 |
| Grant date | May 6, 2014 |
| Priority date | — |
| Expiry date | Jul 28, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0998
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a circuit includes a voltage-controlled oscillator (VCO) configured to generate k first clock signals that each have a first phase based on a charge-pump control voltage signal; one or more phase interpolators (PIs) configured to receive the k first clock signals and one or more first feedback controls signals and generate m second clock signals that each have a second phase based on the k first clock signals and the one or more first feedback control signals; a first phase detector (PD) configured to receive the m second clock signals and generate the one or more first feedback control signals based on the m second clock signals; a second PD configured to generate one or more second feedback control signals based on the m second clock signals; and a charge pump configured to output the charge-pump control voltage signal based on the second feedback control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.