Method and apparatus for executing a program by an SPI interface memory
US8719517B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2010 |
| Grant date | May 6, 2014 |
| Priority date | — |
| Expiry date | Oct 23, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-channel SPI interface memory controller disposed between a CPU and a multi-channel SPI interface memory is provided in the present invention. The multi-channel SPI interface memory controller comprises: a data path interface coupled to a bus of the CPU; a control path interface coupled to the bus of the CPU; a master controller coupled to the multi-channel SPI interface memory; a register bank disposed between the master controller and the control path interface, wherein the master controller is in signal coupling with the data path interface, and in signal coupling through the register bank with the control path interface. The inventive multi-channel SPI interface memory controller can support direct execution of a program on the SPI interface memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.