Method for overcoming livelock in a multi-threaded system
US8719555B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2008 |
| Grant date | May 6, 2014 |
| Priority date | — |
| Expiry date | Jan 3, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor pipeline arrangement 1 includes a plurality of functional units P1, P2, P3, . . . , PN. A number of the functional units P1, P3, PN have access to a respective cache memory C1, C3, CN from which it can retrieve data needed to process threads that pass through the pipeline. The pipeline arrangement 1 also includes a number of monitors to determine when the system enters a state of livelock (e.g. inter-cache livelocks, intra-cache livelocks and/or “near-livelock” situations): a top-level monitor MT to detect livelock situations in the pipeline as a whole; and second-level (“local”) monitors M1 and M3 associated with individual caches C1 and C3.If the system is determined to have entered a livelock state, e.g. by the top-level monitor MT, the number of threads able to change the contents of one or more of the caches C1, C3, CN is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.