Method, system and apparatus for low-power storage of processor context information
US8719612B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2013 |
| Grant date | May 6, 2014 |
| Priority date | — |
| Expiry date | Jan 8, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for saving and/or retrieving context information of a processor core for a power state transition. The processor core resides in a complex power domain variously transitioning between a plurality of power states. The processor core includes a local context storage area for storage and retrieval of processor core context information. A low power context storage resides in a nominal power domain external to the complex power domain. Context information of the processor core is stored to the low power context storage based on whether a power state transition of the complex power domain includes a transition to power down the processor core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.