Single-wire serial interface with delay module for full clock rate data communication between master and slave devices
US8719613B2 · kind B2 · utility
10Cited by
7References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 25, 2011 |
| Grant date | May 6, 2014 |
| Priority date | — |
| Expiry date | Oct 17, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A circuit comprising a single-wire serial interface (SWSI), a delay module coupled to the SWSI and operable to introduce a delay during a data transmission, the delay being dependent on a local clock (LC) associated with the circuit, wherein the delay enables the circuit to synchronize the data transmission with a device coupled to the SWSI based on the LC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.