Speculative multi-threading for instruction prefetch and/or trace pre-build
US8719806B2 · kind B2 · utility
9Cited by
11References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2010 |
| Grant date | May 6, 2014 |
| Priority date | — |
| Expiry date | May 19, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/433
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread to perform instruction prefetch and/or trace pre-build for the main thread.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.