Silicon interposer including backside inductor
US8723292B2 · kind B2 · utility
0Cited by
2References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2012 |
| Grant date | May 13, 2014 |
| Priority date | — |
| Expiry date | Jul 31, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19042
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a silicon interposer that can reduce the entire area of a semiconductor package and increase the degree of integration by forming inductors at a lower part in addition to an upper part of a silicon substrate. The silicon interposer includes a silicon substrate, an upper inductor layer formed at the upper part of the silicon substrate and a lower inductor layer formed at the lower part of the silicon substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.