Semiconductor device, manufacturing method thereof, electronic device and vehicle
US8723295B2 · kind B2 · utility
1Cited by
8References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2012 |
| Grant date | May 13, 2014 |
| Priority date | — |
| Expiry date | Jun 4, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/856
Abstract
The present invention makes it possible to inhibit an SOA (Safe Operating Area) in a vertical-type bipolar transistor from narrowing. A p-type base layer 150 includes a first peak, a second peak, and a third peak in an impurity profile in the thickness direction. The first peak is located on the topmost surface side of a semiconductor substrate 100. The second peak is located closer to the bottom face side of the semiconductor substrate 100 than the first peak and higher than the first peak. The third peak is located between the first peak and the second peak.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.