Patent · US Active

Correcting for offset-errors in a PLL/DLL

US8723566B1 · kind B1 · utility

2Cited by

0References

20Claims

0Family size

Assignee

Cadence AMS Design India Private Limited · IN

Inventors

Rishi Mathur · Delhi, IN
Jyoti Arya · Pilani, IN
Prasenjit Bhowmik · Bengaluru, IN

Key dates

Filing date	Feb 8, 2013
Grant date	May 13, 2014
Priority date	—
Expiry date	Feb 8, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/087
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

The main feedback loop of a PLL/DLL receives a reference clock and an output clock as inputs, and operates to achieve one or both of a phase and a frequency lock of the output clock with respect to the reference clock. The PLL/DLL includes an RS-latch connected to receive the output clock and the reference clock. The RS-Latch generates a digital output representing a phase difference between the reference clock and the output clock. A correction block in the PLL/DLL receives the digital output and adjusts an electrical characteristic of the main feedback loop by a value that is based on a polarity of the digital output. Effects of offset-errors in the PLL/DLL are thereby minimized or corrected for.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.