Cancellation of dynamic offset in MOS resistors
US8723600B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2013 |
| Grant date | May 13, 2014 |
| Priority date | — |
| Expiry date | Feb 22, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/193
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit utilizes a MOS device in a triode mode of operation and includes a biasing circuit and a MOS device. The MOS device has a drain, a source, and a gate terminal, and is coupled to the biasing circuit. The source terminal, drain terminal, and gate terminal each has a potential and the drain and the source terminals have a resistance. The biasing circuit couples the drain and source terminals of the MOS device to the gate terminal of the MOS device. The biasing circuit couples a DC potential to the gate terminal to adjust the resistance between the source and drain terminals of the MOS device. The resistance between the source and drain terminals is a non-linear function of voltage potentials at the source and drain terminals. The biasing circuit reduces the non-linearity of the resistance between the drain and source terminals by modulating the potential at the gate terminal by a combination of source and drain terminal potentials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.