Multi-step ADC with sub-ADC calibration
US8723706B1 · kind B1 · utility
10Cited by
4References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2012 |
| Grant date | May 13, 2014 |
| Priority date | — |
| Expiry date | Aug 28, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/164
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various embodiments of the invention allow for error calibration in analog-to-digital converters (ADCs) having multiple cascaded ADC stages. The ADC stages exchange information that is utilized in the calibration process. Various embodiments allow for calibration of one stage by utilizing a feedback signal from at least one subsequent stage. Certain embodiments of the invention increase the speed of the calibration process by utilizing coarse and fine sub-ADCs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.