Correlation-based background calibration for reducing inter-stage gain error and non-linearity in pipelined analog-to-digital converters
US8723707B2 · kind B2 · utility
12Cited by
44References
32Claims
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Key dates
| Filing date | Jul 27, 2012 |
| Grant date | May 13, 2014 |
| Priority date | — |
| Expiry date | Jul 27, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/167
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and a corresponding device for calibrating a pipelined analog-to-digital converter (ADC) involve injecting a randomly determined amount of dither into one of a flash component and a multiplying digital-to-analog converter (MDAC) in at least one stage in the ADC. For each stage of the at least one stage a correlation procedure is performed to estimate, based on an output of the ADC, an amount of gain experienced by the injected dither after propagating through the stage. The stage is then calibrated based on its respective gain estimate.
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