Display panel
US8723844B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 1, 2010 |
| Grant date | May 13, 2014 |
| Priority date | — |
| Expiry date | Jul 13, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Noise is reduced at a so-called Q-node and a so-called A-node of shift registers in a gate lines driving block of a scan driven display system so that the display system can be safely operated even at elevated temperatures. A variety of techniques may be used to reduce the noise. A first of the techniques applies charging pulses to the A-node at a rate faster than just once every 2H durations, where 1H is the duration of a single row drive. More specifically, a plurality of so-called inverter circuits, rather than just one are included in each shift register stage and the inverters are operated in synchronism with out of phase clock signals so as to thereby increase the rate at which the A-node is pulsed to a high voltage level. A second technique charges up the Q-node in multiple steps. A third technique pulls down the carry line at times when it does not need to go high. A fourth technique combines one or more of the first through third techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.