Programmable packet processor with flow resolution logic
US8724632B2 · kind B2 · utility
0Cited by
7References
6Claims
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Key dates
| Filing date | Aug 28, 2012 |
| Grant date | May 13, 2014 |
| Priority date | — |
| Expiry date | Oct 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/602
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A programmable packet switching controller has a packet buffer, a pattern match module, a programmable packet classification engine and an application engine. The packet classification engine has a decision tree-based classification logic for classifying a packet. The application engine has a number of programmable sub-engines arrayed in a pipelined architecture. The sub-engines include a source lookup engine, a destination lookup engine and a disposition engine, which are used to make a disposition decision for the inbound packets in a processing pipeline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.