Communication testing circuit, electronic device, receiving circuit, transmitting circuit, semiconductor integrated circuit, and wafer
US8724683B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 26, 2011 |
| Grant date | May 13, 2014 |
| Priority date | — |
| Expiry date | May 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/69
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Provided is a communication testing circuit that includes a transmitting unit including a spread spectrum clock generator that generates a modulated clock signal by modulating a reference clock signal, a pseudo-random binary sequence generator that generates a pseudo-random pattern, and a signal generator that generates a transmission signal by modulating the pseudo-random pattern based on the modulated clock signal, a receiving unit including a clock and data recovery circuit that receives the transmission signal and recovers the pseudo-random pattern from the transmission signal, and a detector that compares the recovered pseudo-random pattern with a preset pseudo-random pattern and outputs a signal indicating error information, and a control unit that counts a number of errors from the signal indicating error information input from the receiving unit and decides a timing margin based on a counting result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.