Power-efficient variable-clock-rate DIGRF interface
US8724758B2 · kind B2 · utility
3Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2012 |
| Grant date | May 13, 2014 |
| Priority date | — |
| Expiry date | May 30, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A method in a communication device includes exchanging data between a Baseband Integrated Circuit (BBIC) and a Radio Frequency Integrated Circuit (RFIC) over a digital interface having a variable clock rate. The clock rate of the digital interface is modified repeatedly during a communication session conducted by the communication device, in response to changes in a current operational state of the communication device during the communication session, to a lowest clock rate that is suitable for the current operational state, so as to reduce a power consumption of the communication device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.