Semiconductor integrated circuit for transmitting and receiving data signals in a source-synchronous scheme
US8726060B2 · kind B2 · utility
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3References
10Claims
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Key dates
| Filing date | Jan 3, 2012 |
| Grant date | May 13, 2014 |
| Priority date | — |
| Expiry date | Jul 27, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An adjustment circuit including tri-state circuits is provided between a transmitter circuit and a receiver circuit. Jitter generated by transmission of a signal over a long-distance interconnect is reduced by being converted into jitter of control signals generated by a pulse generator circuit in the tri-state circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.