Generation of simulated errors for high-level system validation
US8726086B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2013 |
| Grant date | May 13, 2014 |
| Priority date | — |
| Expiry date | Aug 26, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3696
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention enable error simulation for system validation. Errors can be simulated by modifying data presented to the processor as well as generating interrupts consistent with the modified data in the ASIC hardware. Modify logic may be added to the ASIC so when the microprocessor attempts to read a specific address, the modify logic may mask one or more of the data bits returned by the requested address. Address, bit mask, and force value data may be stored in registers to determine which address may be modified, the bit location to be modified, and the value that bit location should be changed to. Selection logic may then determine whether data from the modify logic or the unmodified value from an attached device should be sent to the ASIC interface and on to the microprocessor. A timer may also be used to decouple the setup from the test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.