Architecture, system, method, and computer-accessible medium for eliminating scan performance penalty
US8726109B2 · kind B2 · utility
1Cited by
6References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 2, 2012 |
| Grant date | May 13, 2014 |
| Priority date | — |
| Expiry date | Dec 27, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318541
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Exemplary apparatus, methods, and computer-accessible medium can be provided for transforming a circuit. For example, it is possible to select, from the circuit, at least one scan cell which includes a first multiplexer coupled to a first flip-flop. A second flip-flop and a second multiplexer can be inserted in the circuit. The first multiplexer can be coupled as an input to the second flip-flop, and the second multiplexer can be coupled to the output of the first flip-flop and the second flip-flop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.