Dynamic buffer management in a NAND memory controller to minimize age related performance degradation due to error correction
US8726130B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 1, 2010 |
| Grant date | May 13, 2014 |
| Priority date | — |
| Expiry date | Dec 11, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/152
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output buffer circuit for a non-volatile memory comprises an error check circuit, an error correction circuit, a switch circuit, and three storage circuits. The error check circuit receives the plurality of data bits and the plurality of ECC bits from the non-volatile memory to determine if the plurality of data bits need to be corrected and generates a correction signal. The error correction circuit receives the plurality of data bits and the plurality of ECC bits and generates a plurality of corrected data bits in response to the correction signal. A switch enables the output buffer circuit to concurrently performs operations of error check, error correction, and transfer of data bits out of the output buffer circuit on three distinct pluralities of data bits. The switch allows reallocation of storage circuits to different operations without any data transfer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.