Checksum verification accelerator
US8726132B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2011 |
| Grant date | May 13, 2014 |
| Priority date | — |
| Expiry date | Apr 2, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0072
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method and system for validating a data packet by a network processor supporting a first network protocol and a second network protocol and utilizing shared hardware. The network processor receives a data packet; identifies a network packet protocol for the data packet; and processes the data packet according to the network packet protocol comprising: updating a first register with a first partial packet length specific to the first network protocol; updating a second register with a second partial packet length specific to the second network protocol; and updating a third register with a first checksum computed from fields independent of the network protocol. The system produces a second checksum utilizing a function that combines values from the first register, the second register, and the third register. The system validates the data packet by comparing the data packet checksum to the second checksum.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.