Contact structure and manufacturing method thereof
US8728889B2 · kind B2 · utility
11Cited by
7References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2013 |
| Grant date | May 20, 2014 |
| Priority date | — |
| Expiry date | Mar 14, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes conductive patterns vertically stacked on the substrate and having pad regions extended further at edge portions of the conductive patterns as the conductive patterns descend from an uppermost conductive pattern to a lowermost conductive pattern, a first contact plug disposed on a first pad region of the lowermost conductive pattern, a buffer conductive pattern disposed on a second pad region positioned above the first pad region, and a second contact plug formed on the buffer conductive pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.