Integration substrate with a ultra-high-density capacitor and a through-substrate via
US8729665B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2008 |
| Grant date | May 20, 2014 |
| Priority date | — |
| Expiry date | Jul 30, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/73204
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integration substrate for a system in package comprises a through-substrate via and a trench capacitor wherein with a trench filling that includes at least four electrically conductive capacitor-electrode layers in an alternating arrangement with dielectric layers. —The capacitor-electrode layers are alternatingly connected to a respective one of two capacitor terminals provided on the first or second substrate side. The trench capacitor and the through-substrate via are formed in respective trench openings and via openings in the semiconductor substrate, which have an equal lateral extension exceeding 10 micrometer. This structure allows, among other advantages, a particularly cost-effective fabrication of the integration substrate because the via openings and the trench openings in the substrate can be fabricated simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.