Multi-layered chip electronic component
US8729999B2 · kind B2 · utility
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3References
11Claims
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Key dates
| Filing date | Oct 25, 2012 |
| Grant date | May 20, 2014 |
| Priority date | — |
| Expiry date | Oct 25, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01F27/292
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
There is provided a multi-layered chip electronic component, including: a multi-layered body including a plurality of first magnetic layers on which conductive patterns are formed; and second magnetic layers interposed between the first magnetic layers within the multi-layered body, wherein the conductive patterns are electrically connected to form coil patterns in a stacking direction, and when a thickness of the second magnetic layer is defined as Ts and a thickness of the conductive pattern is defined as Te, 0.1≦Ts:Te≦0.3 is satisfied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.