Optimized multi-level finite state machine with redundant DC nodes
US8730067B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2012 |
| Grant date | May 20, 2014 |
| Priority date | — |
| Expiry date | Nov 21, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/22
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and system for eliminating/suppressing long transition runs over a communications channel is disclosed. The method may include providing modulation coding based on a multi-level finite state machine (ML-FSM) having a periodic structure, the periodic structure being defined by a predetermined number of time frames. The ML-FSM may include a plurality of penalty-free edges for connecting nodes in one time frame to nodes at the same level in a subsequent time frame and a plurality of penalty edges for connecting nodes in one time frame to nodes at an upper level in the subsequent time frame. The method may further include utilizing the ML-FSM based modulation coding to facilitate data transmission over the communications channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.