Systems and methods for providing an analog-to-digital converter that uses reduced power and supply voltage
US8730082B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2011 |
| Grant date | May 20, 2014 |
| Priority date | — |
| Expiry date | Jun 1, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/442
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and systems are described for providing an analog-to-digital converter that uses reduced power and supply voltage. In one embodiment, an analog-to-digital converter comprises a sample phase configured to sample an analog signal with at least three capacitors, wherein at least two of the three capacitors have unequal capacitance to cause the analog-to-digital converter to have a feedback factor that is greater than 1/3. The analog-to-digital converter also includes a feedback phase configured to produce a digital output signal based at least in part on the sampled analog signal, wherein the analog-to-digital converter is configured to operate with a supply voltage equal to about one half of an input signal voltage range of the analog signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.