Providing a reset mechanism for a latch circuit
US8730404B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2012 |
| Grant date | May 20, 2014 |
| Priority date | — |
| Expiry date | Oct 11, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/455
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, the present invention includes a latch circuit having a first input to receive a data signal and a second input to receive a clock signal. This latch circuit may have a first pair of transistors including a first transistor gated by the data signal and a second transistor gated by an inverted data signal and a second pair of transistors including third and fourth transistors gated by the clock signal. The first transistor may be coupled to the third transistor at a first inter-latch node and the second transistor coupled to the fourth transistor at a second inter-latch node. A reset circuit may be coupled to the latch circuit to maintain the first and second inter-latch nodes at a predetermined voltage level when the clock signal is inactive.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.