SRAM cell writability
US8730713B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2012 |
| Grant date | May 20, 2014 |
| Priority date | — |
| Expiry date | Aug 20, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for detecting and improving writeability of a static random access memory (SRAM) cell. A bias voltage value corresponding to an operating condition, such as, a process, a voltage, or a temperature operation condition that indicates a cell write failure condition of an external SRAM array comprising the SRAM cell is generated. This bias voltage value is applied to word lines of SRAM cells in a model SRAM array. A first delay for a trigger signal rippled through the model SRAM array is detected and compared to a reference delay. A write assist indication is generated if the first delay is greater than or equal to the reference delay. Based on the write assist indication, a write assist is provided to the SRAM cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.