Signal separating circuit, signal separating method, signal multiplexing circuit and signal multiplexing method
US8731006B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2011 |
| Grant date | May 20, 2014 |
| Priority date | — |
| Expiry date | Jan 30, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4904
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
When a data signal of a first channel is an RZ signal having a pulse period T1 and a logic “1” pulse width m, a data signal of a second channel is an RZ signal having a pulse period T2 and a logic “1” pulse width n and the relation n<m is satisfied, a multiplexed signal D obtained by time-division multiplexing the data signals of two channels is input. A pulse signal with a pulse width k satisfying n<k<min(m, T2) is generated at timing of a leading edge of the data signal of each channel. When the multiplexed signal D is judged as logic “1” at timing of a trailing edge of the pulse signal, the data signal of the first channel is output. Similarly, when the multiplexed signal D is judged as logic “0”, the data signal of the second channel is output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.