Parallel closed-loop DFE filter architecture
US8731041B2 · kind B2 · utility
1Cited by
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19Claims
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Key dates
| Filing date | Apr 18, 2012 |
| Grant date | May 20, 2014 |
| Priority date | — |
| Expiry date | Apr 28, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03566
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A DFE filter includes an input, a first filter loop coupled to the input for providing an odd bit-stream, and a second filter loop coupled to the input for providing an even bit-stream, wherein the first and second filter loops are identical and interleaved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.