Two-stage intrusion detection system for high-speed packet processing using network processor and method thereof
US8732833B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2012 |
| Grant date | May 20, 2014 |
| Priority date | — |
| Expiry date | Jun 15, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L63/0245
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system and method for detecting network intrusion by using a network processor are provided. The intrusion detection system includes: a first intrusion detector, configured to use a first network processor to perform intrusion detection on layer 3 and layer 4 of a protocol field among information included in a packet header of a packet transmitted to the intrusion detection system, and when no intrusion is detected, classify the packets according to stream and transmit the classified packets to a second intrusion detector; and a second intrusion detector, configured to use a second network processor to perform intrusion detection through deep packet inspection (DPI) for the packet payload of the packets transmitted from the first intrusion detector. Thereby, intrusion detection for high-speed packets can be performed in a network environment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.