Semiconductor device having diffusion barrier element injection region
US8735951B2 · kind B2 · utility
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2References
19Claims
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Key dates
| Filing date | Dec 16, 2011 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Feb 28, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/667
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes an isolation pattern disposed on a substrate, the isolation pattern defining an active part, a gate pattern crossing the active part on the substrate, the gate pattern including a dielectric pattern and a first conductive pattern, and the dielectric pattern being between the active part and the first conductive pattern, a pair of doping regions in the active part adjacent to side walls of the gate pattern, the gate pattern being between the pair of doping regions, and a diffusion barrier element injection region disposed in an upper region of the active part.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.