Vertical MOSFET transistor with a vertical capacitor region
US8735957B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 16, 2012 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Jul 16, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Consistent with an example embodiment, there is a package that includes a first voltage terminal, and a second voltage terminal, a first die including a first MOSFET having a drain region electrically connected to the first voltage terminal and further having a source region, A second die is adjacent to the first die, the second die includes a second MOSFET having a drain region electrically connected to the source region of the first MOSFET and having a source region electrically connected to the second voltage terminal. The semiconductor package further includes a vertical capacitor having a first plate electrically connected to the drain region of the first MOSFET and a second plate electrically connected to the source region of the second MOSFET and the second plate is electrically insulated from the first plate by a dielectric material. The capacitor is integrated on the first die or the second die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.