Self-biased high speed level shifter circuit
US8736304B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 30, 2005 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Nov 19, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018507
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for translating signals between different components located in different power boundaries in a mixed voltage system. A level shifter system includes a first level shifter circuit connected to a first voltage source. A second level shifter circuit connects to a second voltage source. An intermediate level shifter circuit has an input that connects to the output of the first level shifter circuit. The output of the intermediate level shifter circuit connects to the input of the second level shifter circuit. The intermediate level shifter circuit uses an intermediate voltage source having an intermediate voltage about midway between the first voltage of the first voltage source and the second voltage of the second voltage source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.