Patent · US Active

Systems and methods for providing duty cycle correction

US8736329B1 · kind B1 · utility

15Cited by

5References

27Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Yashar Rajavi · San Jose, US
Shahram Abdollahi-Alibeik · Menlo Park, US
Hakan Dogan · Berkeley, US

Key dates

Filing date	Feb 6, 2013
Grant date	May 27, 2014
Priority date	—
Expiry date	Feb 6, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH03K5/1565
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Systems and methods are disclosed including a duty cycle module having two timer circuits to measure pulse widths of a clock signal. Two comparators are used to generate control signals depending upon comparisons of the pulse width measurements. In response to the control signals, either the clock signal or an inverted clock signal may be programmably delayed such that combination of the clock signal and the inverted clock signal results in a corrected clock signal. Systems and methods are also disclosed for verifying operation of a duty cycle module.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.